Ceramic multilayer chip capacitor and method for making
US5097391A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1990 |
| Grant date | Mar 17, 1992 |
| Priority date | — |
| Expiry date | Oct 18, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/435
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In a ceramic multilayer chip capacitor comprising alternately stacked internal electrodes of Ni or Ni alloy and dielectric layers, an oxide layer having a different composition from the dielectric layer is formed on the periphery of each internal electrode. The dielectric layer consists essentially of grains and a grain boundary phase, the percent area of the grain boundary phase being up to 2% of the area of a cross section of the dielectric layer. The capacitor is prepared by alternately stacking Ni or Ni alloy and a dielectric material in layer form, firing and then heat treating the stack under predetermined oxygen partial pressures. The dielectric material is a barium titanate base oxide material. The capacitor has a long effective life.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.