Method and apparatus for designing integrated circuits
US5097422A · kind A · utility
282Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1989 |
| Grant date | Mar 17, 1992 |
| Priority date | — |
| Expiry date | Jun 29, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for determining integrated circuit layouts from a virtual circuit description and specification of a technology. Starting with high-level descriptions of a circuit, a virtual geometric description of the circuit is developed using a virtual grid described in terms of reference points relative to a substrate surface. The relationships among the reference points are expressed as fractions of variables that can also be used to define the design rules. When the technology is specified, the relationships among the reference points is determined, as in the layout of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.