Registered RAM array with parallel and serial interface
US5099481A · kind A · utility
55Cited by
7References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1989 |
| Grant date | Mar 24, 1992 |
| Priority date | — |
| Expiry date | Feb 28, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial protocol register and an initialization counter are configured to initialize (program) a RAM array. The register is configured to receive, in serial format, an initial address to be loaded into the counter. Also, the register is configured to receive, in serial format, a series of machine states (data words), each to be stored in the RAM array. In addition, the register is configured to clock the counter following each received machine state. The counter is configured to develop a series of addresses, each for accessing the RAM array to store in the array a corresponding one of the machine states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.