Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefrom
US5100817A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1991 |
| Grant date | Mar 31, 1992 |
| Priority date | — |
| Expiry date | Jul 12, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
A stacked semiconductor structure including a base structure (18/19) is comprised of a semiconductor substrate having active regions (21) of devices (N1, . . . ) formed therein and/or a plurality of polysilicon lines (23-1, . . . ) formed thereupon; a first thick passivating layer (26/27) having a set of first metal contact studs (30-1, . . . ) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, . . . ), the surface of said first metal contact studs being coplanar with the surface of said first thick passivating layer; a plurality of first polysilicon lands (31-1, . . . ) formed on the said thick passivating layer, certain portions of said first polysilicon lands defining the source, drain and channel regions forming the body of a PFET device with at least one region (SP1) contacting one of said first metal contact studs; a thin insulating layer (33) forming the gate dielectric layer of said PFET device; a plurality of highly doped second polysilicon lands (35-1A, . . . ) formed over by said thin insulating layer (33); a certain portion of said second polysilicon lands (35-1A, . . . ) forming the gate electrode (GP1) of said PFET device …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.