Digital data regeneration and deserialization circuits
US5101203A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1990 |
| Grant date | Mar 31, 1992 |
| Priority date | — |
| Expiry date | Jun 29, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A substantially simultaneous digital data regeneration and deserialization technique for communication systems and information and data processing systems is disclosed. A digital phase lock logic circuit (DPLL) receives the serial stream of clock and data bits at its input and outputs a plurality of clock signals with different phase. A plurality of latches are coupled to receive a respective one of the clock output signals from the DPLL. Each latch receives the serial stream of clock and data bits through a second input such that the latches are sequentially set by substantially simultaneously received clock and data information at the two inputs and the serial data bits within the stream appear as parallel data bits at the latch outputs. Enhanced versions of this circuit are also described, along with an alternate embodiment which uses an analog phase locked loop circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.