Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5101341A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1988 |
| Grant date | Mar 31, 1992 |
| Priority date | — |
| Expiry date | Sep 2, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanwhile, an operand execute pipeline retrieves such entries from the FIFO buffer as needed, using the predecoded instruction bits to rapidly decode and execute the instructions at rates determined by the instructions themselves. Delays due to cache misses are substantially or entirely masked, as the instructions and associated predecoded bits are loaded into the FIFO buffer more rapidly than they are retrieved from it, except during cache misses. A method is described for increasing the effective speed of executing a three operand construct. Another method is disclosed for increasing the effective speed of executing a loop containing a branch instruction by scanning the predecoded bits in establishing a link between successive instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.