Data processor having split level control store
US5101344A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1990 |
| Grant date | Mar 31, 1992 |
| Priority date | — |
| Expiry date | Jul 25, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor having a split level control store structure, which partitions program memory into a macrocode portion and a microcode portion. The data processor contains two distinct machines, a macromachine and a micromachine. The macromachine includes an instruction sequence controller which detects the macrocode branch instruction before it is perceived by the micromachine, extracts from the branch instruction a macroaddress, and then provides the extracted macroaddress to the program memory as the next sequential instruction address. By "pipelining" the macromachine, the macromachine can "execute" the branch instruction in parallel with, and independent of, the execution by the micromachine of the preceeding instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.