I/O structure for information processing system
US5101478A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 1988 |
| Grant date | Mar 31, 1992 |
| Priority date | — |
| Expiry date | Aug 4, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components. The communications to SPUs all require a single SPU bus cycle; the communications to system components require one or more cycles. The system bus interface translates communicat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.