Hexagonal mesh multiprocessor system
US5101480A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 1989 |
| Grant date | Mar 31, 1992 |
| Priority date | — |
| Expiry date | May 9, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17343
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interconnection network for a plurality of process nodes, each illustratively comprised of a processor-memory pair, utilizes an hexagonal mesh arrangement of size n which is wrapped in each of the x, y, and z directions. In accordance with the invention, a unique address value is assigned to each processor node in the network, beginning at a central processor node and continuing along the x direction, and via the wrapping links, until each such processor node has a unique sequential address. Each of the rows, having first and last processor nodes therein, is wrapped by coupling each of the last processor nodes in each row to a respective first processor node in a corresponding row which is n-1 rows away. Point-to-point communication is achieved using the unique addresses of only the source and destination processor nodes, without requiring each intermediate processor node to contain global information about the entire network. An algorithm computes the shortest path between the source and destination processor nodes, in terms of the minimum number of processors which must be encountered by the message as it proceeds along the x, y, and z directions of the network toward the dest…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.