Vertical DRAM cell and method
US5102817A · kind A · utility
102Cited by
40References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1990 |
| Grant date | Apr 7, 1992 |
| Priority date | — |
| Expiry date | Nov 26, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
DRAM cells and arrays of cell on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trech sidewalls with word lines and bit lines crossing over the cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.