Circuit technique for creating predetermined duty cycle
US5103114A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 19, 1990 |
| Grant date | Apr 7, 1992 |
| Priority date | — |
| Expiry date | Mar 19, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for allowing a clock of any specified duty cycle to be created from a clock of the same frequency using standard digital delay lines. In particular, an EXOR function is implemented to generate a clock signal having a frequency which is twice the frequency of its input signals by using standard logic components such that the active branch for each input edge has an independent path to the output signal. In this manner, if a time delay is introduced into the active branch and only the active branch, the corresponding output edge and only that edge will be delayed by a like amount. Over a complete cycle of the input waveforms, four output edges are produced (two clock cycles). By varying the delay on the input branches, these output edges can be placed independently and arbitrarily within the period. As such, an output waveform having any desired duty cycle can be created independent of the phase relationship between the two input waveforms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.