Input buffer regenerative latch for ECL levels
US5103121A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1990 |
| Grant date | Apr 7, 1992 |
| Priority date | — |
| Expiry date | Apr 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356017
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An imput buffer regenerative latch circuit useful in BiCMOS integrated circuits is presented. The ECL input signal terminal is connected to the base of a bipolar transistor. The emitter of the transistor is connected to one of two input/out nodes of a CMOS regenerative latch circuit by the source/drain path of a MOS transistor. The second input/output node is similar connected to the emitter of a second bipolar transistor by the source/drain path of a second MOS transistor. The base of the second bipolar transistor is held at a reference voltage midway in the ECL voltage range. Latching occurs very quickly when the CMOS latch is activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.