High speed low power DC offsetting circuit
US5103122A · kind A · utility
6Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1990 |
| Grant date | Apr 7, 1992 |
| Priority date | — |
| Expiry date | Aug 21, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45479
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed, low power DC-offsetting circuit, comprising: an amplifier having an inverting input, a non-inverting input which is adapted to be connected to a high speed low DC voltage source and having an output; a current source which is connected to said inverting input and through a bypass resistor to said output; and capacitor means and resistor means, connected in series with each other at an output node, for connecting said non-inverting input to said output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.