Plural-order sigma-delta analog-to-digital converters using both single-bit and multiple-bit quantization
US5103229A · kind A · utility
63Cited by
4References
29Claims
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Key dates
| Filing date | Apr 23, 1990 |
| Grant date | Apr 7, 1992 |
| Priority date | — |
| Expiry date | Apr 23, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/414
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oversampling converter of a type using a plural-order, plural-stage sigma-delta modulator, the output signal to the decimating filter of which modulator has the quantization noise contribution of a number of its plurality of stages suppressed therein, uses single-bit quantization in those stages to help avoid problems of nonlinearity. Each other sigma-delta converter stage, the quantization noise of which appears in substantial amount in the converter output signal to the decimating filter, uses quantization having multiple-bit resolution to help increase the resolution of the oversampling converter overall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.