Programmable digital filter
US5103416A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1989 |
| Grant date | Apr 7, 1992 |
| Priority date | — |
| Expiry date | Nov 21, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2017/0692
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The digital filter includes a plurality of parallel adders, each whereof has a first input, a second input and an output; the parallel output of each adder is connected to the first input of the successive adder across a respective delay element. The second input of each adder is connected in parallel to the output of one of a plurality of memory banks, each whereof comprises a plurality of addressable memory cells, the addressing inputs whereof can be driven by a sampled digital signal to be filtered, and the memory cells of each bank contain a digital value which is equal to the product of a preset coefficient by the address of the cell itself.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.