Dynamic random access memory and a method of operating the same
US5103423A · kind A · utility
13Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1991 |
| Grant date | Apr 7, 1992 |
| Priority date | — |
| Expiry date | Feb 20, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic RAM includes a memory cell comprised of a data read transistor, a data write transistor and a data storage capacitor. The data write transistor is turned on in response to a row selection signal to connect the capacitor to a write bit line. The dynamic RAM includes a structure for shifting the level of potential of internal write data to be transmitted onto the write bit line. This structure will prevent the data write transistor from being turned on by the undershoot produced on the write bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.