Delay equalization detector
US5105439A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1989 |
| Grant date | Apr 14, 1992 |
| Priority date | — |
| Expiry date | Aug 11, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04H20/67
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An improved method for detecting that a facility delay has changed is provided. According to the invention, a facility having a delay that may change is coupled to a transmitter and a receiver. The transmitter is coupled to a first clock that transmits a first signal based on its current reading (the first clock signal) from time to time to the receiver via the facility. The receiver is coupled to a second clock that generates a second signal based on its current reading (the second clock signal) responsive to receiving the first clock signal. In operation, the first clock signal is fed downstream (via the facility having the delay), thereby triggering the second clock signal. The two clock signals are then detected and the difference in the two clock readings computed, thereby forming .DELTA..sub.n. The process is then repeated for successive first and second clock signals, thereby forming .DELTA..sub.n+1. The absolute value of .DELTA..sub.n -.DELTA..sub.n+a is then compared with a predetermined value to determine whether the facility time delay has changed. This method is particularly useful in simulcast broadcast systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.