Self timed register file having bit storage cells with emitter-coupled output selectors for common bits sharing a common pull-up resistor and a common current sink
US5107462A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1989 |
| Grant date | Apr 21, 1992 |
| Priority date | — |
| Expiry date | Feb 3, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self time register (STREG) 44 is constructed on a single custom ECL integrated circuit and has provisions for generating its own internal clock signal. The STREG 44 includes a set of latches 80a-80q for temporarily storing the data delivered thereto concurrent with the system clock pulse. Thereafter, the internally generated clock pulse (W.sub.PULS) controls the write operation of the temporary latches into the STREG 44. The STREG has data storage registers including bit storage cells which receive the data in response to the internally generated clock pulse. To selectively output the data, the bit storage cells have emitter-coupled output selectors, and the output selectors for common bits share a common current sink and a common pull-up resistor at which a single-bit output signal is provided from a selected register. Preferably, each bit storage cell has a first output selector for a first data output port, and a second output selector for a second data output port. By sharing of a common pull-up resistor and a current sink for each bit position of each output port, an economy of components can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.