Electrostatic discharge protection devices for semiconductor chip packages
US5108299A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 1991 |
| Grant date | Apr 28, 1992 |
| Priority date | — |
| Expiry date | Apr 18, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A plurality of electrostatic discharge (hereafter referred to as "ESD") protection devices are disclosed for use with semiconductor chip packaging (hereafter referred to as "SCP") of the type having a top surface, a bottom surface, and, disposed between the top and bottom surface, a plurality of interface surfaces having a plurality of connector pins disposed thereon. In one embodiment, the ESD protection device comprises a base section secured to the top surface of the SCP and a plurality of integral shorting arms each extending outward from the top surface in spaced apart relationship with respect to each other and in spaced apart alignment with respect each of the connector pins. Each shorting arm has a first portion which is integral to the base section and a distal end portion integrally connected with the first portion and extending outwardly therefrom. The first portion is wider than the distal end portion and this defines a transverse edge portion which is yieldably biased by the shorting arm against a respective connector pin thereby creating an electrical connection therebetween. The plurality of connector pins subsequent insertion into corresponding complementary recepta…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.