Testing circuit for semiconductor memory array
US5109257A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 1989 |
| Grant date | Apr 28, 1992 |
| Priority date | — |
| Expiry date | Dec 27, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test circuit is incorporated in a semiconductor memory device including at least one ultraviolet erasable and electrically programmable non-volatile memory cell having a control gate and a floating gate. The test circuit comprises a switching circuit for selectively supplying the control gate of the memory cell with a voltage which is higher than a power supply voltage for ordinary reading a content of the memory cell, through a write voltage supply line used for writing data to the memory cell. The switching circuit makes it possible to test the written state of the memory cell with a voltage different from the normal reading power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.