Microprocessor which terminates bus cycle when access address falls within a predetermined processor system address space
US5109492A · kind A · utility
9Cited by
12References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1987 |
| Grant date | Apr 28, 1992 |
| Priority date | — |
| Expiry date | Aug 13, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor suitable for a high speed processor system prevents extension of a bus cycle due to delay of generation of a bus cycle end signal and effectively utilizes a characteristic of a high speed accessable external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.