Method and apparatus for executing concurrent CO processor operations and precisely handling related exceptions
US5109514A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 1990 |
| Grant date | Apr 28, 1992 |
| Priority date | — |
| Expiry date | Aug 1, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system which includes a central processing unit including a first processing unit that performs basic processing functions and a co-processing unit that performs multiple specialized processing functions concurrently with the first processing unit, an arrangement for detecting the occurrence of a function causing an exception in a result produced by the coprocessing unit, an arrangement for specifying to the first processing unit any exception in a result produced by the coprocessing unit, an arrangement for using the first processing unit to implement any function which causes an exception in a result produced by the co-processing unit, an arrangement for storing the identification of the instruction being handled by the first processing unit when a function causing any exception in a result produced by the co-processing unit occurs, and an arrangement for determing the instruction which produced the exception.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.