Image frame buffer access speedup by providing multiple buffer controllers each containing command FIFO buffers
US5109520A · kind A · utility
57Cited by
8References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 16, 1987 |
| Grant date | Apr 28, 1992 |
| Priority date | — |
| Expiry date | Nov 16, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/022
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A frame buffer memory controller allows rapid image updating while maintaining screen refresh data flow rate. One frame buffer memory controller controls one or more pixel depth columns comprising one or more frame buffer memory chips per pixel. Each frame buffer memory controller listens on a display processor bus for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer for execution during the first free memory cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.