Silicon membrane with controlled stress
US5110373A · kind A · utility
75Cited by
8References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 9, 1990 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Aug 9, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method for fabricating a silicon membrane with predetermined stress characteristics. A silicon substrate is doped to create a doped layer as thick as the desired thickness of the membrane. Stress within the doped layer is controlled by selecting the dopant based on its atomic diameter relative to silicon and controlling both the total concentration and concentration profile of the dopant. The membrane is then formed by electrochemically etching away the substrate beneath the doped layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.