Method of manufacturing a semiconductor device including forming a flattening layer over hollows in a contact hole
US5110766A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1990 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Jul 6, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device, in particular a contact portion of the wiring of the device. An insulating layer is formed on a semiconductor substrate, a contact hole is formed on the insulating layer by etching, and a first conductive layer having hollows is formed on the insulating layer and in the contact hole. Next, a flattening layer is formed to flatten the surface of device structure, and a part of the first conductive layer is exposed by etching the flattening layer to permit a part of the flattening layer to remain in hollows of device structure. Next, a second conductive layer is formed on the remaining flattening layer and the exposed part of the first conductive layer, and is connected to the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.