Layout of integrated circuit with very large transistors
US5111069A · kind A · utility
15Cited by
3References
100Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1991 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Mar 27, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit which provides multiple independently accessible low-on-state-resistance switches, using conventional CMOS technology. Charge pumping is used to boost the gate voltage to lower the on-state resistance. The surface of the chip consists primarily of a few very large path transistors. This chip is perferably combined with a power management chip which provides logic outputs, and the large PMOS switches are used for controlling the power supply to various other chips, such as SRAMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.