Adjusting delay circuitry
US5111086A · kind A · utility
10Cited by
2References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 19, 1990 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Nov 19, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00097
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Gate speed evaluation circuitry evaluates the operating speed of gates of a calibration network and adjusts the length of a tapped delay network on the same chip to provide uniform delay in a signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.