Chip form of surface mounted electrical resistance and its manufacturing method
US5111179A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1990 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Oct 22, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01C17/006
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The chip form electrical resistance is designed to be soldered notably on a printed circuit card or on an hybrid circuit substratum. It includes an electrically insulating substratum (1) of the ceramic type, to which is attached by a layer of adhesive organic resin (2) a sheet of metal or of resistive alloy (3) which is engraved to provide a sinuous resistance. The layer of resin (6) leaves in the area of the two opposite sides of the substratum (1), two free areas (5), at the extremities of the engraved resistive sheet (3). These two parts (5) of the resistive sheet are each covered by a thin layer (8) of a metal or alloy adhering to the resistive sheet (3), this layer (8) being covered by a second thicker layer (9) of metal or conductive alloy, and this second layer (9) being covered by a third, also thicker layer (14) of a solderable metal, these three superimposed layers (8, 9, 14) spreading equally over both lateral sides opposite the substratum (1) and partially on its face (13) opposite the engraved resistive sheet (3).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.