Trench capacitor memory cell with curved capacitors
US5111259A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1989 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Jul 25, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/37
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. In another embodiment of the present invention, a planar capacitor is used with a field plate isolation scheme including a transfer transistor moat region self-aligned to the field plate. This structure allows the elimination of alignment tolerances between the capacitor and the transistor thus reducing the space necessary between the transistor and the capacitor. In another embodiment of the present invention, a memory cell using two conductive plates formed inside a trench as the storage capacitor is fabricated. A field plate isolation scheme which allows for self-alignment of the moat containing the transfer transistor is used thus allowing for self-alignment of the moat and elimination of alignment tolerances between the moat region and the source drain diffusions. In addition, a sidewall insulator technique using two different …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.