System for performing addition and subtraction of signed magnitude floating point binary numbers
US5111421A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1990 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Feb 26, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A versatile floating point adder which performs high speed floating point addition or subtraction on operands supplied in a signed magnitude format includes separate exponent and mantissa data paths for processing the exponent fields and mantissa fields of the floating point binary numbers to be added or subtracted. The exponent data path computes the absolute difference between the exponents of the floating point numbers, passes the large exponent, and adjusts the large exponent by an amount needed to normalize the mantissa and to reflect an overflow in the mantissa addition/substration and mantissa rounding operations. The mantissa data path denormalizes one of the input mantissas, adds the two mantissas after the denormalization operation, post-normalizes the resulting mantissa, and rounds the mantissa to the correct precision.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.