Interleaved time-division multiplexor with phase-compensated frequency doublers
US5111455A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1990 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Aug 24, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/047
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A synchronous, interleaved, time-division M:1 multiplexor. Following an input stage of parallel synchronous latches for latching M incoming parallel data bits (where M is an integer power of two equal to or greater than four) is an intermediate stage of parallel synchronous latches. The intermediate latches are clocked with selected phases of an M-phase clock having M equally-spaced phases of a clock signal having a frequency of B/M (where B is the outgoing bit rate) to latch each bit at a time at least 2/B (i.e., two outgoing bit periods) after such bit is received from its respective input latch. A first stage of 2:1 multiplexors, following the intermediate latches and used to begin multiplexing the latched bits, are clocked with selected phases of the M-phase clock to begin multiplexing each bit at a time at least 1/B (i.e., one outgoing bit period) after such bit is received from its respective intermediate latch. Further stages of 2:1 multiplexors complete the multiplexing and are each clocked with clock signals which are successively doubled in frequency at each additional stage of 2:1 multiplexors (e.g., 2B/M, 4B/M, 8B/M, . . . ) and phase compensated so as to align the cloc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.