Bit synchronizer
US5111486A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1989 |
| Grant date | May 5, 1992 |
| Priority date | — |
| Expiry date | Mar 15, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A paging receiver capable of bit synchronizing to one of two data rates. The receiver has a digital phase locked loop integrated onto a single integrated circuit clocked by a single frequency crystal. The paging receiver receives and synchronizes to a POCSAG signal which may be transmitted at either 512 bits per second or 1200 bits per second. The digital phase locked loop bit synchronizes to either data rate using a single crystal frequency of 76.8 kHz. The data rate is selected by a bit in the code paging receiver's code plug. The digital phase locked loop is constructed to have a substantially constant frequency to bandwidth ratio at both data rates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.