BiCMOS circuit
US5113096A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1991 |
| Grant date | May 12, 1992 |
| Priority date | — |
| Expiry date | Apr 2, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A BiCMOS logic circuit which implements single stage inverting and non-inverting logic functions is described. The circuit includes pull-up and pull-down assembly means coupled between the input and the non-inverting output nodes. The pull-down assembly means comprises a pair of complimentary metal-oxide semiconductor field-effect transistors connected in an inverter configuration in which the gates of the pair of CMOS transistors are coupled to the input node while the output of the inverter configuration provides the inverting output while driving the gate of a n-channel transistor coupled between the non-inverting output node and V.sub.ss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.