Semiconductor memory apparatus with a spare memory cell array
US5113371A · kind A · utility
35Cited by
2References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 26, 1990 |
| Grant date | May 12, 1992 |
| Priority date | — |
| Expiry date | Jul 26, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a test of a fabricated semiconductor memory chip, a test control signal is supplied to a test control circuit, so that a spare memory cell array is tested whether spare memory cells are functionable for writing and reading of data. The test control signal is applied to terminals which are used for the supplying of an address signal, etc. For this purpose, the test control signal has a level different from that of the address signal. Therefore, the spare memory cell array can be tested simultaneously with a test of normal memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.