System having an address generating unit and a log comparator packaged as an integrated circuit seperate from cache log memory and cache data memory
US5113506A · kind A · utility
51Cited by
12References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1990 |
| Grant date | May 12, 1992 |
| Priority date | — |
| Expiry date | Mar 9, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache-based computer architecture is disclosed in which the address generating unit and the tag comparator are packaged together and separately from the cache RAMs. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and the tag busses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.