Method and apparatus for handling faults of vector instructions causing memory management exceptions
US5113521A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1991 |
| Grant date | May 12, 1992 |
| Priority date | — |
| Expiry date | Jan 9, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system handles memory management exceptions caused by a faulting vector instruction in a vector processor by halting the execution of the faulting vector instruction being executed when the exception occurred and by setting the state information for the vector processor to acknowledge the presence of the exception and to include information about the suboperation of the vector instruction being executed when the exception occurred. The scalar processor is not interrupted at this time, however. Any other vector instructions executing simutaneously with the faulting vector instruction are allowed to continue so long as those instructions do not require data from the faulting instruction. The faulting partially completed vector instruction resumes execution after the operating system has processed the memory management exception.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.