Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
US5115510A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1988 |
| Grant date | May 19, 1992 |
| Priority date | — |
| Expiry date | Oct 19, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4494
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processor includes a program memory for storing a data flow program having destination information and instruction information as one set. Destination information, instruction information and operand data included in an input data packet are latched in an input data latching portion. Only the operand data is transferred to an output data latching portion. An address is operated based on the destination information latched in the input data latching portion, and the program memory is accessed, so that the data flow program is read out. The destination information and the instruction information included in the read data flow program are latched in the output data latching portion. Paired data is detected by a paired data detection portion based on the data flow program latched in the output data latching portion. The detected data is operated by an operation processing portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.