Customizable logic integrated circuit with multiple-drain transistor for adjusting switching speed
US5117127A · kind A · utility
3Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1990 |
| Grant date | May 26, 1992 |
| Priority date | — |
| Expiry date | Sep 28, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a logic integrated circuit for which the time of switching over between two logic states, 0 and 1, is adjustable. In a logic operator such as an inverter, the switch-over time, at the output, is a function of the current put through by the load transistor or by the signal transistor. This time is adjustable, either as rising time or as fall time, by the replacement of at least one single-drain transistor by a multiple-drain transistor, the throughput rate of which is fixed by the number of connected drains. The disclosed device can be applied to pre-diffused (Si) circuits or pre-implanted (GaAs) circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.