CMOS or TTL to ECL level conversion device
US5117134A · kind A · utility
5Cited by
6References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1990 |
| Grant date | May 26, 1992 |
| Priority date | — |
| Expiry date | Aug 24, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017563
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The semiconductor level conversion device for an ECL circuit having a pair of transistors connected commonly at their emitters. A first gate circuit is connected to apply a first output signal to a base of one of the transistors, and a second gate circuit is connected to apply a second output signal to a base of the other of the transistors. The first and second output signals are held in-phase relation to each other. The first output signal has a high logic level lower than that of the second output signal and a low logic level higher than that of the second output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.