Memory address mechanism in a distributed memory architecture
US5117350A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1988 |
| Grant date | May 26, 1992 |
| Priority date | — |
| Expiry date | Dec 15, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having plural nodes interconnected by a common broadcast bus. Each node has memory and at least one node has a processor. The system has a dynamically configurable memory which may be located within the system address space of a distributed system architecture including memory within each node having a processor and the memory resident within other nodes. The memory in the system address space is addressable by system physical addresses which are isolated from the physical addresses for memory in each node. The node physical addresses are translatable to and from the system physical addresses by partition maps located in partition tables at each node. Memory located anywhere in the distributed system architecture may be partitioned dynamically and accessed on a local basis by programming the partition tables, stored in partitioning RAMs. The use of the partitioning process permits data to be duplicated throughout a distributed system architecture and permits read cycles for shared data to execute at local bus speeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.