Packet switch for a transfer of data in asynchronous mode in a digital transmission network
US5117429A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 1989 |
| Grant date | May 26, 1992 |
| Priority date | — |
| Expiry date | Aug 1, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/30
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The packet switch for asynchronous mode transfer in a transmission network is organized around a multiplexed bus which absorbs all the throughput. For this, the incoming trunk lines are connected to an 8-bit series/parallel adapter made with fast technology elements, followed by memory stacks associated with the incoming trunk lines, from which the pieces of data are removed at moderate speed in wider packets. A multiplexer transmits these pieces of data to the central bus. At this level, a centralized translation of the headers is done. Then the pieces of data are transmitted to the outgoing channels through a reversed structure, with output memory stacks restoring 8-bit words at moderate speed, and then an adapting circuit transmitting the series data at high speed to the outgoing arteries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.