Microprogram controlled microprocessor having a selectively expandable instruction code length including independent description of operand addressing and a type of operation for an operand by single instruction in a common coding scheme
US5117488A · kind A · utility
20Cited by
7References
4Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 1, 1988 |
| Grant date | May 26, 1992 |
| Priority date | — |
| Expiry date | Nov 1, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30156
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length. One feature of the invention is that an instruction set which can selectively expand the instruction code length at a unit of the predetermined number of bits is used. Another feature is that an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.