Ring reduction logic using parallel determination of ring numbers in a plurality of functional units and forced ring numbers by instruction decoding
US5117491A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1989 |
| Grant date | May 26, 1992 |
| Priority date | — |
| Expiry date | Mar 31, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
During the execution of an instruction by an execution unit, the instruction is stored in an instruction register, the operand including its ring number is stored in a data register and the ring number developed by the Virtual Memory Management Unit is stored in a ring effective register. The instruction addresses a control store which stores a firmware word in a control store register. A firmware field is decoded to generate a plurality of ring control signals. The ring numbers from the data and ring effective registers are compared and an effective ring number is generated. Depending on the states of the secure process signal, the ring control signals and the relative value of the ring numbers, the effective ring number is binary 00 or the larger ring number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.