Pipelined register cache
US5117493A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 1989 |
| Grant date | May 26, 1992 |
| Priority date | — |
| Expiry date | Aug 7, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined register cache for increasing a computer processor's execution speed by reducing the time required to access register data. A register cache is implemented to keep often-used registers in high-speed storage immediately available to the processor's arithmetic and logic unit (ALU). The register cache is constructed using a number of individual register stages which are connected in series such that the register information contained in each register stage is passed from one register stage to the next in a First-In, First-Out (FIFO) queue arrangement. Each register stage stores a register address tag for identifying the particular primary register being represented in that register stage, and a data value representing the actual register contents. When a register that is not represented in the cache is needed for a calculation, the register information is first loaded from the primary register storage into the first register stage of the register cache. Once the register is represented in register cache, it can be accessed quickly by the arithmetic and logic unit for computations. As new register information is loaded into the register cache, the older register information…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.