Emitter coupled logic circuit having independent input transistors
US5118973A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1990 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Aug 22, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved emitter coupled logic circuit suitable for high speed logic operation independent of capacitive load. With previous circuits as the load to be driven become heavier, the capacitive load required a longer time for discharge and the output signal was dulled, resulting in adverse effect on the logic operation when the output changed to a low level from a high level. A pulse has also been previously applied to a pull-down transistor connected between the output and a power source through a capacitor from an inverted phase output to actively discharge the capacitive load. However, when the capacitor is connected to the output it hinders the switching speed of a current switch. In the present invention, a transistor is provided an input circuit and a pulse is applied to a pull-down transistor from the transistor. As a result, an extra capacitive element is not connected to the output end, but a pulse is applied to the pull-down transistor. Accordingly, even if the capacitive load becomes heavier, the speed of the circuit is not harmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.