Tristate circuits with fast and slow OE signals
US5118974A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1990 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Jul 19, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0826
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A FAST OE signal circuit generates FAST OE signals of high and low potential levels. A SLOW OE signal circuit generates SLOW OE signals corresponding to FAST OE signals. The SLOW OE signals have the same high or low potential level as the corresponding FAST OE signals and occur a specified time delay after the corresponding FAST OE signals. A tristate output buffer circuit operates in the bistate mode when enabled by high potential level OE signals for transmitting binary data signals, and operates in a high Z tristate mode when disabled by low potential level OE signals. The FAST OE signal circuit and SLOW OE signal circuit ae coupled in parallel to the tristate output buffer circuit for enabling and disabling the tristate output buffer circuit. The FAST and SLOW OE signals in combination skew the enable time relative to the disable time. The enable times tpZH and tpZL are substantailly longer than the disable times tpHZ and tpLZ, introducing "temporal" separation between active tristate output devices on a common bus to reduce bus contention. A DC Miller killer circuit is coupled to the pulldown transistor element of the tristate output buffer circuit for turning off and holding …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.