Digital clock buffer circuit providing controllable delay
US5118975A · kind A · utility
115Cited by
34References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1990 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Mar 5, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.