Gate array semiconductor integrated circuit device
US5119158A · kind A · utility
10Cited by
5References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 20, 1990 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Nov 20, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
A set of input and output buffers are arranged in an outer peripheral portion of a semiconductor chip and a macro region and a set of internal gates are arranged in an inside portion of the semiconductor chip. The input and output buffers are connected to the internal gates through a boarder region between the macro and the set of the internal gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.