Semiconductor integrated circuit device using a planar structure with reduced bit line and word line resistance
US5119165A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 3, 1991 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Jul 3, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device which comprises a substrate, a first continuous longitudinal diffusion layer formed in the substrate and a second continuous longitudinal diffusion layer constitutes source areas of a plurality of MOS transistors. The second diffusion layer constitutes drain areas of the transistors. The device further comprises a first polycide layer formed on and along each of the first and second diffusion layers in contact therewith and a second polycide layer for constituting a gate electrode of each of the transistors. The second polycide layer is formed on and transversing the first polycide layers in a direction perpendicular to the first and second diffusion layers. An insulation layer is interposed between the first and second polycide layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.