Semiconductor die having rounded or tapered edges and corners
US5119171A · kind A · utility
18Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1991 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | Mar 22, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
Abstract
An improved semiconductor die for plastic encapsulated semiconductor device packages which impedes the inherent delamination caused by the differing expansion coefficients of the semiconductor die and plastic encapsulation. Rounded or tapered die corners and die edges decrease the stress from the plastic encapsulation that acts upon the semiconductor die. This reduced stress slows the delamination progression and leaves the operational circuitry unaffected for an increased period of time thereby increasing device lifetime.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.